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- 000 03120cam a2200337 i 4500
- 008 200321s2020 sz a b 001 0 eng d
- 020 __ |z 9783030387969 |q ebook
- 020 __ |z 3030387968 |q ebook
- 035 __ |a (OCoLC)1143642374 |z (OCoLC)1142899482 |z (OCoLC)1151723688 |z (OCoLC)1152548824 |z (OCoLC)1153167174 |z (OCoLC)1153950973 |z (OCoLC)1154483986
- 035 __ |a springerebks3030387968
- 040 __ |a EBLCP |b eng |e rda |c EBLCP |d GW5XE |d YDX |d OCLCQ |d LQU |d OCLCF |d UKAHL |d UKMGB
- 100 1_ |a Jain, Saurabh, |e author.
- 245 10 |a Adaptive digital circuits for power-performance range beyond wide voltage scaling : |b from the clock path to the data path / |c Saurabh Jain, Longyang Lin, Massimo Alioto.
- 260 __ |a Cham : |b Springer, |c 2020.
- 300 __ |a xvi, 166 pages : |b illustrations ; |c 25 cm
- 336 __ |a text |b txt |2 rdacontent
- 337 __ |a unmediated |b n |2 rdamedia
- 338 __ |a volume |b nc |2 rdacarrier
- 504 __ |a Includes bibliographical references and index.
- 520 __ |a This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical). Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained. Provides extensive coverage of the challenges and the key technologies enabling wide power-performance range in digital sub-systems (e.g., processors, memories, accelerators); Includes in-depth description of silicon-proven methodologies to design reconfigurable data path and clock path; Describes techniques for reconfigurable microarchitectures, down to the pipestage and the clock repeater level; Uses a highly interdisciplinary approach covering the circuit, the microarchitectural and the system levels of abstraction; Presents practical design examples and the related methodologies; Offers complementary design files and scripts, useful to replicate the presented developments and develop new designs.
- 650 _0 |a Digital electronics.
- 700 1_ |a Alioto, Massimo, |e author.
- 700 1_ |a Lin, Longyang, |e author.